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Texas Instruments /MSP432P411Y /SYSCTL_A /SYS_PERIHALT_CTL

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Interpret as SYS_PERIHALT_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HALT_T16_0_0)HALT_T16_0 0 (HALT_T16_1_0)HALT_T16_1 0 (HALT_T16_2_0)HALT_T16_2 0 (HALT_T16_3_0)HALT_T16_3 0 (HALT_T32_0_0)HALT_T32_0 0 (HALT_eUA0_0)HALT_eUA0 0 (HALT_eUA1_0)HALT_eUA1 0 (HALT_eUA2_0)HALT_eUA2 0 (HALT_eUA3_0)HALT_eUA3 0 (HALT_eUB0_0)HALT_eUB0 0 (HALT_eUB1_0)HALT_eUB1 0 (HALT_eUB2_0)HALT_eUB2 0 (HALT_eUB3_0)HALT_eUB3 0 (HALT_ADC_0)HALT_ADC 0 (HALT_WDT_0)HALT_WDT 0 (HALT_DMA_0)HALT_DMA 0 (HALT_LCD_0)HALT_LCD

HALT_eUA2=HALT_eUA2_0, HALT_WDT=HALT_WDT_0, HALT_LCD=HALT_LCD_0, HALT_eUB2=HALT_eUB2_0, HALT_ADC=HALT_ADC_0, HALT_eUA1=HALT_eUA1_0, HALT_T16_3=HALT_T16_3_0, HALT_eUB3=HALT_eUB3_0, HALT_T32_0=HALT_T32_0_0, HALT_eUB1=HALT_eUB1_0, HALT_T16_2=HALT_T16_2_0, HALT_T16_0=HALT_T16_0_0, HALT_DMA=HALT_DMA_0, HALT_eUA3=HALT_eUA3_0, HALT_eUA0=HALT_eUA0_0, HALT_eUB0=HALT_eUB0_0, HALT_T16_1=HALT_T16_1_0

Description

Peripheral Halt Control Register

Fields

HALT_T16_0

Freezes IP operation when CPU is halted

0 (HALT_T16_0_0): IP operation unaffected when CPU is halted

1 (HALT_T16_0_1): freezes IP operation when CPU is halted
HALT_T16_1

Freezes IP operation when CPU is halted

0 (HALT_T16_1_0): IP operation unaffected when CPU is halted

1 (HALT_T16_1_1): freezes IP operation when CPU is halted
HALT_T16_2

Freezes IP operation when CPU is halted

0 (HALT_T16_2_0): IP operation unaffected when CPU is halted

1 (HALT_T16_2_1): freezes IP operation when CPU is halted
HALT_T16_3

Freezes IP operation when CPU is halted

0 (HALT_T16_3_0): IP operation unaffected when CPU is halted

1 (HALT_T16_3_1): freezes IP operation when CPU is halted
HALT_T32_0

Freezes IP operation when CPU is halted

0 (HALT_T32_0_0): IP operation unaffected when CPU is halted

1 (HALT_T32_0_1): freezes IP operation when CPU is halted
HALT_eUA0

Freezes IP operation when CPU is halted

0 (HALT_eUA0_0): IP operation unaffected when CPU is halted

1 (HALT_eUA0_1): freezes IP operation when CPU is halted
HALT_eUA1

Freezes IP operation when CPU is halted

0 (HALT_eUA1_0): IP operation unaffected when CPU is halted

1 (HALT_eUA1_1): freezes IP operation when CPU is halted
HALT_eUA2

Freezes IP operation when CPU is halted

0 (HALT_eUA2_0): IP operation unaffected when CPU is halted

1 (HALT_eUA2_1): freezes IP operation when CPU is halted
HALT_eUA3

Freezes IP operation when CPU is halted

0 (HALT_eUA3_0): IP operation unaffected when CPU is halted

1 (HALT_eUA3_1): freezes IP operation when CPU is halted
HALT_eUB0

Freezes IP operation when CPU is halted

0 (HALT_eUB0_0): IP operation unaffected when CPU is halted

1 (HALT_eUB0_1): freezes IP operation when CPU is halted
HALT_eUB1

Freezes IP operation when CPU is halted

0 (HALT_eUB1_0): IP operation unaffected when CPU is halted

1 (HALT_eUB1_1): freezes IP operation when CPU is halted
HALT_eUB2

Freezes IP operation when CPU is halted

0 (HALT_eUB2_0): IP operation unaffected when CPU is halted

1 (HALT_eUB2_1): freezes IP operation when CPU is halted
HALT_eUB3

Freezes IP operation when CPU is halted

0 (HALT_eUB3_0): IP operation unaffected when CPU is halted

1 (HALT_eUB3_1): freezes IP operation when CPU is halted
HALT_ADC

Freezes IP operation when CPU is halted

0 (HALT_ADC_0): IP operation unaffected when CPU is halted

1 (HALT_ADC_1): freezes IP operation when CPU is halted
HALT_WDT

Freezes IP operation when CPU is halted

0 (HALT_WDT_0): IP operation unaffected when CPU is halted

1 (HALT_WDT_1): freezes IP operation when CPU is halted
HALT_DMA

Freezes IP operation when CPU is halted

0 (HALT_DMA_0): IP operation unaffected when CPU is halted

1 (HALT_DMA_1): freezes IP operation when CPU is halted
HALT_LCD

Freezes IP operation when CPU is halted

0 (HALT_LCD_0): IP operation unaffected when CPU is halted

1 (HALT_LCD_1): freezes IP operation when CPU is halted

Links

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Register License

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Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data